Design and TCAD simulation of planar p-on-n active-edge pixel sensors for the next generation of FELs

Gamma-ray response of SOI bipolar junction transistors for fast, radiation tolerant front-end electronics

article

Response of SOI bipolar transistors exposed to /spl gamma/-rays under different dose rate and bias conditions

article

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Design criteria for low noise front-end electronics in the 0.13μm CMOS generation

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers

article

Review of radiation damage studies on DNW CMOS MAPS

Design of Time Invariant Analog Front-End Circuits for Deep N-Well CMOS MAPS

Characterization of bandgap reference circuits designed for high energy physics applications

Proton-induced damage in JFET transistors and charge preamplifiers on high-resistivity silicon

article

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

Front-end performance and charge collection properties of heavily irradiated DNW MAPS

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

scholarly article published 2007

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Radiation hardness test of FSSR, a multichannel, mixed signal chip for microstrip detector readout

High accuracy injection circuit for the calibration of a large pixel sensor matrix

Design of low-power, low-voltage, differential I/O links for High Energy Physics applications

High accuracy injection circuit for pixel-level calibration of readout electronics

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

In-pixel conversion with a 10 bit SAR ADC for next generation X-ray FELs

Triple Well CMOS Active Pixel Sensor with In-Pixel Full Signal Analog

Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

A study for the detection of ionizing particles with phototransistors on thick high-resistivity silicon substrates

Noise analysis of NPN SOI bipolar transistors for the design of charge measuring systems

article

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

First prototype of a silicon microstrip detector with the data-driven readout chip FSSR2 for a tracking-based trigger system

The PixFEL project: Progress towards a fine pitch X-ray imaging camera for next generation FEL facilities

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

scientific article

JFET front-end circuits integrated in a detector-grade silicon substrate

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

Front-End Performance and Charge Collection Properties of Heavily Irradiated DNW MAPS

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

130 and 90nm CMOS technologies for detector front-end applications

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

CMOS MAPS in a homogeneous 3D process for charged particle tracking

Performance of a DNW CMOS active pixel sensor designed for the ILC Vertex Detector

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

Analog Front-End for the Readout of LGAD-Based Particle Detectors

scientific article published in October 2024

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Time invariant analog processors for monolithic deep n-well CMOS pixel detectors

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

A 3D deep n-well CMOS MAPS for the ILC vertex detector