The readout of the LHC beam luminosity monitor: accurate shower energy measurements at a repetition rate

Minimum noise design of charge amplifiers with CMOS processes in the 100 nm feature size range

Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies

PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs

JFET preamplifiers with different reset techniques on detector-grade high-resistivity silicon

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Proposal of a data sparsification unit for a mixed-mode MAPS detector

A new approach to the design of monolithic active pixel detectors in triple well CMOS technology

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging

Radiation effects on the noise parameters of a 0.18 μm CMOS technology for detector front-end applications

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

Pixel-level continuous-time analog signal processing for 130nm CMOS MAPS

scholarly article by Gianluca Traversi et al published March 2007 in Nuclear Instruments and Methods in Physics Research

High precision injection circuit for in-pixel calibration of a large sensor matrix

Low-noise readout channel with a novel dynamic signal compression for future X-FEL applications

The associative memory for the self-triggered SLIM5 silicon telescope

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC

Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology

Total ionizing dose effects on the analog performance of a 0.13μm CMOS technology

Vertical integration approach to the readout of pixel detectors for vertexing applications

Noise Performance of 0.13$mu$m CMOS Technologies for Detector Front-End Applications

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

Performance of a high accuracy injection circuit for in-pixel calibration of a large sensor matrix

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

scientific article

Recent results from the development of silicon detectors with integrated electronics

65-nm CMOS Front-End Channel for Pixel Readout in the HL-LHC Radiation Environment

Comprehensive Study of Total Ionizing Dose Damage Mechanisms and Their Effects on Noise Sources in a 90 nm CMOS Technology

Correction to "Selection criteria for F and N-channel JFETs as input elements in low-noise radiation-hard charge preamplifiers"

scholarly article published in IEEE Transactions on Nuclear Science

Channel hot carrier stress on irradiated 130-nm NMOSFETs: Impact of bias conditions during X-ray exposure

article

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

Effects of γ-rays on JFET devices and circuits fabricated in a detector-compatible process

Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-μm CMOS generation

Selection criteria for P- and N-channel JFETs as input elements in low-noise radiation-hard charge preamplifiers

Recent progress in the development of 3D deep n-well CMOS MAPS

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

article

65 nm CMOS analog front-end for pixel detectors at the HL-LHC

Development of deep N-well monolithic active pixel sensors in a CMOS technology

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

Introducing 65nm CMOS technology in low-noise read-out of semiconductor detectors

Fast analog front-end for the readout of the SuperB SVT inner Layers

Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100nm frontier