A Circuit Synthesis Flow for Controllable-Polarity Transistors

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A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

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A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells

article by Pierre-Emmanuel Gaillardon et al published October 2015 in IEEE Transactions on Very Large Scale Integration Systems

A PLiM Computer for the Internet of Things

A Survey on Low-Power Techniques with Emerging Technologies

A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs

A fast pruning technique for low-power inexact Circuit design

A study on buffer distribution for RRAM-based FPGA routing structures

Accurate power analysis for near-V t RRAM-based FPGA

An FPGA-Based Test System for RRAM Technology Characterization

An MIG-based compiler for programmable logic-in-memory architectures

BDS-MAJ

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form

Computationally Efficient Multiple-Independent-Gate Device Model

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Endurance management for resistive Logic-In-Memory computing architectures

scholarly article published March 2017

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Exact Synthesis of Majority-Inverter Graphs and Its Applications

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Introduction to the special section on functionality-enhanced devices

Logic Synthesis for Majority Based In-Memory Computing

Logic Synthesis for RRAM-Based In-Memory Computing

Majority Logic Synthesis for Spin Wave Technology

Majority-Inverter Graph

Majority-Inverter Graph: A New Paradigm for Logic Optimization

Multiple Independent Gate FETs: How many gates do we need?

NEM relay design with biconditional binary decision diagrams

Nanowire systems: technology and design

scientific article published on 24 February 2014

New Logic Synthesis as Nanotechnology Enabler

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

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Post-P&R Performance and Power Analysis for RRAM-Based FPGAs

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams

Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs

scientific article published on 30 March 2017

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

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