Analyzing Functional Coverage in Bounded Model Checking

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm

Approximation-aware rewriting of AIGs for error tolerant applications

Automatic Fault Localization for SystemC TLM Designs

Compiled symbolic simulation for systemC

Completeness-Driven Development

article

Debugging Contradictory Constraints in Constraint-Based Random Simulation

article

Debugging reversible circuits

Designing a RISC CPU in Reversible Logic

Equivalence Checking of Reversible Circuits

Exact sat-based toffoli network synthesis

GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development

scientific article published on 31 May 2023

Improvements for constraint solving in the systemc verification library

article published in 2007

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation

Precise error determination of approximated components in sequential circuits with model checking

article

ProACt

Processor Verification

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

article published in 2008

Quality-Driven SystemC Design

scholarly article published 2010

Reversible Logic Synthesis with Output Permutation

SAT-Lancer

Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction

Simulation-based equivalence checking between SystemC models at different levels of abstraction

System level validation using formal techniques

The system verification methodology for advanced TLM verification

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

Verifying SystemC using an intermediate verification language and symbolic simulation

WoLFram- A Word Level Framework for Formal Verification

Yise - a novel framework for boolean networks using y-inverter graphs