List of works - Lodovico Ratti

The BABAR detector

scientific article

Properties and performance of the prototype instrument for the Pierre Auger Observatory

article

The SLIM5 low mass silicon tracker demonstrator

article published in 2010

The superB silicon vertex tracker

A 4096-pixel MAPS device with on-chip data sparsification

Design and characterization of integrated front-end transistors in a micro-strip detector technology

article

Feasibility studies of microelectrode silicon detectors with integrated electronics

The SuperB silicon vertex tracker

Low-noise design criteria for detector readout systems in deep submicron CMOS technology

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

Sensor performance of the BaBar Silicon Vertex Tracker after 4 years of data taking

A bilinear analog compressor to adapt the signal dynamic range in the AUGER fluorescence detector

The high rate data acquisition system for the SLIM5 beam test

article published in 2010

A novel monolithic active pixel detector in triple well CMOS technology with pixel level analog processing

article published in 2006

Beam test results for the SuperB-SVT thin striplet detector

Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configurations

A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

article published in 2016

The analog signal processor of the Auger fluorescence detector prototype

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

Crosstalk mapping in CMOS SPAD arrays

article published in 2016

Monolithic pixel detectors in a CMOS technology with sensor level continuous time charge amplification and shaping

The front-end chip of the SuperB SVT detector

Submicron CMOS technologies for low-noise analog front-end circuits

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

Erratum to: Sensor performance of the BaBar Silicon Vertex Tracker after 4 years of data taking

scholarly article published in Nuclear Instruments and Methods in Physics Research

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

Erratum to: “Low-noise design criteria for detector readout systems in deep submicron CMOS technology”

scholarly article published in Nuclear Instruments and Methods in Physics Research

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

A fabrication process for silicon microstrip detectors with integrated front-end electronics

Thin pixel development for the SuperB silicon vertex tracker

BaBar silicon vertex tracker: Status and prospects

Design and test of clock distribution circuits for the Macro Pixel ASIC

article published in 2016

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

Performance of the BABAR silicon vertex tracker

article published in 2003

Low-power clock distribution circuits for the Macro Pixel ASIC

article published in 2015

Comparison of ionizing radiation effects in 0.18 and 0.25 μm cmos technologies for analog applications

article published in 2003

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

article published in 2012

PixFEL: Enabling technologies, building blocks and architectures for advanced X-ray pixel cameras at the next generation FELs

article published in 2014

Recent developments in 130 nm CMOS monolithic active pixel detectors

Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

Monolithic Active Pixel Sensors in a 130 nm Triple Well CMOS Technology

Status and future plans of the BABAR Silicon Vertex Tracker

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

2D and 3D CMOS MAPS with high performance pixel-level signal processing

scholarly article by Gianluca Traversi et al published February 2011 in Nuclear Instruments and Methods in Physics Research

List of works by Lodovico Ratti

The BABAR detector

Properties and performance of the prototype instrument for the Pierre Auger Observatory

The SLIM5 low mass silicon tracker demonstrator

The superB silicon vertex tracker

A 4096-pixel MAPS device with on-chip data sparsification

Design and characterization of integrated front-end transistors in a micro-strip detector technology

Feasibility studies of microelectrode silicon detectors with integrated electronics

The SuperB silicon vertex tracker

Low-noise design criteria for detector readout systems in deep submicron CMOS technology

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

Sensor performance of the BaBar Silicon Vertex Tracker after 4 years of data taking

A bilinear analog compressor to adapt the signal dynamic range in the AUGER fluorescence detector

The high rate data acquisition system for the SLIM5 beam test

A novel monolithic active pixel detector in triple well CMOS technology with pixel level analog processing

Beam test results for the SuperB-SVT thin striplet detector

Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configurations

A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

The analog signal processor of the Auger fluorescence detector prototype

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

Crosstalk mapping in CMOS SPAD arrays

Monolithic pixel detectors in a CMOS technology with sensor level continuous time charge amplification and shaping

The front-end chip of the SuperB SVT detector

Submicron CMOS technologies for low-noise analog front-end circuits

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

Erratum to: Sensor performance of the BaBar Silicon Vertex Tracker after 4 years of data taking

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

Erratum to: “Low-noise design criteria for detector readout systems in deep submicron CMOS technology”

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

A fabrication process for silicon microstrip detectors with integrated front-end electronics

Thin pixel development for the SuperB silicon vertex tracker

BaBar silicon vertex tracker: Status and prospects

Design and test of clock distribution circuits for the Macro Pixel ASIC

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

Performance of the BABAR silicon vertex tracker

Low-power clock distribution circuits for the Macro Pixel ASIC

Comparison of ionizing radiation effects in 0.18 and 0.25 μm cmos technologies for analog applications

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

PixFEL: Enabling technologies, building blocks and architectures for advanced X-ray pixel cameras at the next generation FELs

Recent developments in 130 nm CMOS monolithic active pixel detectors

Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

Monolithic Active Pixel Sensors in a 130 nm Triple Well CMOS Technology

Status and future plans of the BABAR Silicon Vertex Tracker

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

2D and 3D CMOS MAPS with high performance pixel-level signal processing

TID effects in deep N-well CMOS monolithic active pixel sensors

The BaBar Silicon Vertex Tracker: Performance, running experience and radiation damage studies

An improved fabrication process for Si-detector-compatible JFETs

A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT