130 and 90nm CMOS technologies for detector front-end applications

2D and 3D CMOS MAPS with high performance pixel-level signal processing

scholarly article by Gianluca Traversi et al published February 2011 in Nuclear Instruments and Methods in Physics Research

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

3D DNW MAPS for high resolution, highly efficient, sparse readout CMOS detectors

65-nm CMOS Front-End Channel for Pixel Readout in the HL-LHC Radiation Environment

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

A 3D deep n-well CMOS MAPS for the ILC vertex detector

A 4096-pixel MAPS device with on-chip data sparsification

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

article published in 2012

A new approach to the design of monolithic active pixel detectors in triple well CMOS technology

A novel monolithic active pixel detector in triple well CMOS technology with pixel level analog processing

article published in 2006

A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

Advantages of a vertical integration process in the design of DNW MAPS

Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

Beam test results for the SuperB-SVT thin striplet detector

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

CMOS MAPS in a homogeneous 3D process for charged particle tracking

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

Characterization of Bulk Damage in CMOS MAPS With Deep N-Well Collecting Electrode

Characterization of bandgap reference circuits designed for high energy physics applications

Characterization of bulk damage in CMOS MAPS with deep N-well collecting electrode

Charge Signal Processors in a 130 nm CMOS Technology for the Sparse Readout of Small Pitch Monolithic and Hybrid Pixel Sensors

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Comparison of ionizing radiation effects in 0.18 and 0.25 μm cmos technologies for analog applications

article published in 2003

Comprehensive Study of Total Ionizing Dose Damage Mechanisms and Their Effects on Noise Sources in a 90 nm CMOS Technology

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

Design criteria for low noise front-end electronics in the 0.13μm CMOS generation

Design of Time Invariant Analog Front-End Circuits for Deep N-Well CMOS MAPS

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

scholarly article published 2006

Development of deep N-well monolithic active pixel sensors in a CMOS technology

Effects of Substrate Thinning on the Properties of Quadruple Well CMOS MAPS

Effects of γ-rays on JFET devices and circuits fabricated in a detector-compatible process

Evaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics

Fast analog front-end for the readout of the SuperB SVT inner Layers

First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100nm frontier

Front-End Performance and Charge Collection Properties of Heavily Irradiated DNW MAPS

Front-end electronics in a 65nm CMOS process for high density readout of pixel sensors

Front-end performance and charge collection properties of heavily irradiated DNW MAPS

Gamma-ray response of SOI bipolar junction transistors for fast, radiation tolerant front-end electronics

article

Heavily Irradiated 65-nm Readout Chip With Asynchronous Channels for Future Pixel Detectors

High accuracy injection circuit for pixel-level calibration of readout electronics

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

Introducing 65nm CMOS technology in low-noise read-out of semiconductor detectors

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

Ionizing Radiation Effects on the Noise of 65 nm CMOS Transistors for Pixel Sensor Readout at Extreme Total Dose Levels

article

JFET front-end circuits integrated in a detector-grade silicon substrate

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

article

Minimum noise design of charge amplifiers with CMOS processes in the 100 nm feature size range

Modeling Charge Loss in CMOS MAPS Exposed to Non-Ionizing Radiation

Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

Monolithic pixel detectors in a CMOS technology with sensor level continuous time charge amplification and shaping

Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology

Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Noise Performance of 0.13$mu$m CMOS Technologies for Detector Front-End Applications

Noise Performances of 0.13 μm CMOS Technologies for Detector Front-end Applications

Noise analysis of NPN SOI bipolar transistors for the design of charge measuring systems

article

Non-Standard Approach to Charge Signal Processing in CMOS MAPS for Charged Particle Trackers

scholarly article

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

Optimization of signal extraction and front-end design in a fast, multigap ionization chamber

Performance of a DNW CMOS active pixel sensor designed for the ILC Vertex Detector

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs

Pixel-level continuous-time analog signal processing for 130nm CMOS MAPS

scholarly article by Gianluca Traversi et al published March 2007 in Nuclear Instruments and Methods in Physics Research

Proposal of a data sparsification unit for a mixed-mode MAPS detector

Proton-induced damage in JFET transistors and charge preamplifiers on high-resistivity silicon

article

Quadruple Well CMOS MAPS With Time-Invariant Processor Exposed to Ionizing Radiation and Neutrons

Quadruple well CMOS MAPS with time-invariant processor exposed to ionizing radiation and neutrons

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

Radiation effects on the noise parameters of a 0.18 μm CMOS technology for detector front-end applications

Radiation hardness test of FSSR, a multichannel, mixed signal chip for microstrip detector readout

Recent developments in 130 nm CMOS monolithic active pixel detectors

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

Recent progress in the development of 3D deep n-well CMOS MAPS

Recent results from the development of silicon detectors with integrated electronics

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

Response of SOI bipolar transistors exposed to /spl gamma/-rays under different dose rate and bias conditions

article

Review of radiation damage studies on DNW CMOS MAPS

Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

TID effects in deep N-well CMOS monolithic active pixel sensors

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

The SLIM5 low mass silicon tracker demonstrator

article published in 2010

The SuperB silicon vertex tracker

The associative memory for the self-triggered SLIM5 silicon telescope

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

The front-end chip of the SuperB SVT detector

The high rate data acquisition system for the SLIM5 beam test

article published in 2010

The readout of the LHC beam luminosity monitor: accurate shower energy measurements at a repetition rate

The superB silicon vertex tracker

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

Thin pixel development for the SuperB silicon vertex tracker

Time invariant analog processors for monolithic deep n-well CMOS pixel detectors

Total ionizing dose effects on the analog performance of a 0.13μm CMOS technology

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

Triple Well CMOS Active Pixel Sensor with In-Pixel Full Signal Analog

Vertical integration approach to the readout of pixel detectors for vertexing applications

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging