List of works - Luigi Gaioni

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

Review of radiation damage studies on DNW CMOS MAPS

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

scholarly article published 2007

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Design of low-power, low-voltage, differential I/O links for High Energy Physics applications

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

scientific article

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

CMOS MAPS in a homogeneous 3D process for charged particle tracking

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

A 3D deep n-well CMOS MAPS for the ILC vertex detector

Front-end electronics in a 65nm CMOS process for high density readout of pixel sensors

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

Advantages of a vertical integration process in the design of DNW MAPS

List of works by Luigi Gaioni

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

Review of radiation damage studies on DNW CMOS MAPS

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Design of low-power, low-voltage, differential I/O links for High Energy Physics applications

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

CMOS MAPS in a homogeneous 3D process for charged particle tracking

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

A 3D deep n-well CMOS MAPS for the ILC vertex detector

Front-end electronics in a 65nm CMOS process for high density readout of pixel sensors

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

Advantages of a vertical integration process in the design of DNW MAPS