The SLIM5 low mass silicon tracker demonstrator

article published in 2010

The superB silicon vertex tracker

A 4096-pixel MAPS device with on-chip data sparsification

The SuperB silicon vertex tracker

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

The high rate data acquisition system for the SLIM5 beam test

article published in 2010

Beam test results for the SuperB-SVT thin striplet detector

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

The front-end chip of the SuperB SVT detector

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

Thin pixel development for the SuperB silicon vertex tracker

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

Low-power clock distribution circuits for the Macro Pixel ASIC

article published in 2015

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

article published in 2012

Recent developments in 130 nm CMOS monolithic active pixel detectors

Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

2D and 3D CMOS MAPS with high performance pixel-level signal processing

scholarly article by Gianluca Traversi et al published February 2011 in Nuclear Instruments and Methods in Physics Research

TID effects in deep N-well CMOS monolithic active pixel sensors

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

Evaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics

3D DNW MAPS for high resolution, highly efficient, sparse readout CMOS detectors

Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies

Upgrade of the Belle II vertex detector with depleted monolithic CMOS active pixel sensors

scientific article published in November 2025

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

The associative memory for the self-triggered SLIM5 silicon telescope

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

Vertical integration approach to the readout of pixel detectors for vertexing applications

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

scientific article

Comprehensive Study of Total Ionizing Dose Damage Mechanisms and Their Effects on Noise Sources in a 90 nm CMOS Technology

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

Recent progress in the development of 3D deep n-well CMOS MAPS

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

article

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

Introducing 65nm CMOS technology in low-noise read-out of semiconductor detectors

Fast analog front-end for the readout of the SuperB SVT inner Layers

Modeling Charge Loss in CMOS MAPS Exposed to Non-Ionizing Radiation

Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100nm frontier