List of works - Luigi Gaioni

2D and 3D CMOS MAPS with high performance pixel-level signal processing

scholarly article by Gianluca Traversi et al published February 2011 in Nuclear Instruments and Methods in Physics Research

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

3D DNW MAPS for high resolution, highly efficient, sparse readout CMOS detectors

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

A 3D deep n-well CMOS MAPS for the ILC vertex detector

A 4096-pixel MAPS device with on-chip data sparsification

A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

article published in 2012

Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

Advantages of a vertical integration process in the design of DNW MAPS

Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology

Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

Beam test results for the SuperB-SVT thin striplet detector

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

scholarly article by Eugenio Paoloni et al published February 2011 in Nuclear Instruments and Methods in Physics Research

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

CMOS MAPS in a homogeneous 3D process for charged particle tracking

CMOS technologies in the 100nm range for rad-hard front-end electronics in future collider experiments

Charge signal processors in sparse readout CMOS MAPS and hybrid pixel sensors for the SuperB Layer0

Comprehensive Study of Total Ionizing Dose Damage Mechanisms and Their Effects on Noise Sources in a 90 nm CMOS Technology

Deep n-well MAPS in a 130nm CMOS technology: Beam test results

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Design of low-power, low-voltage, differential I/O links for High Energy Physics applications

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

scientific article

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

Evaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics

Fast analog front-end for the readout of the SuperB SVT inner Layers

First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100nm frontier

Front-end electronics in a 65nm CMOS process for high density readout of pixel sensors

Impact of gate-leakage current noise in sub-100 nm CMOS front-end electronics

Introducing 65nm CMOS technology in low-noise read-out of semiconductor detectors

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

Latest results of the R&D on CMOS MAPS for the Layer0 of the SuperB SVT

Low-power clock distribution circuits for the Macro Pixel ASIC

article published in 2015

Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

article

Modeling Charge Loss in CMOS MAPS Exposed to Non-Ionizing Radiation

Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology

Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

Perspectives for low noise detector readout in a sub-quarter-micron CMOS SOI technology

Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

scholarly article published 2007

Recent developments in 130 nm CMOS monolithic active pixel detectors

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

Recent progress in the development of 3D deep n-well CMOS MAPS

Review of radiation damage studies on DNW CMOS MAPS

Review of radiation effects leading to noise performance degradation in 100 - nm scale microelectronic technologies

SLIM5 beam test results for thin striplet detector and fast readout beam telescope

TID Effects in Deep N-Well CMOS Monolithic Active Pixel Sensors

TID effects in deep N-well CMOS monolithic active pixel sensors

TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs

The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node

The SLIM5 low mass silicon tracker demonstrator

article published in 2010

The SuperB silicon vertex tracker

The associative memory for the self-triggered SLIM5 silicon telescope

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

The front-end chip of the SuperB SVT detector

The high rate data acquisition system for the SLIM5 beam test