A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques

A New Approach to Software-Implemented Fault Tolerance

A P1500-compatible programmable BIST approach for the test of embedded flash memories

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries

A System-layer Infrastructure for SoC Diagnosis

A new hybrid fault detection technique for systems-on-a-chip

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

Combined software and hardware techniques for the design of reliable IP processors

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

Embedded Memory Diagnosis: An Industrial Workflow

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

Evaluating system dependability in a co-design framework

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

Experiences in the use of evolutionary techniques for testing digital circuits

Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors

Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores

Exploiting an I-IP for in-field SOC test

scientific article

Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Exploiting circuit emulation for fast hardness evaluation

GALLO: a genetic algorithm for floorplan area optimization

GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

Guaranteeing testability in re-encoding for low power

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Identification and classification of single-event upsets in the configuration memory of sram-based fpgas

Impact of data cache memory on the single event upset-induced error rate of microprocessors

Improved software-based processor control-flow errors detection technique

Initializability analysis of synchronous sequential circuits

Integrating BIST techniques for on-line SoC testing

Investigation of Interference Models for RFID Systems.

scientific article published on 4 February 2016

New techniques for efficiently assessing reliability of SOCs

Nonlinear Predictive Threshold Model for Real-Time Abnormal Gait Detection

scientific article published on 26 June 2018

On the Automation of the Test Flow of Complex SoCs

On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core

Safety Evaluation of NanoFabrics

Software and Hardware Techniques for SEU Detection in IP Processors

System safety through automatic high-level code transformations: an experimental evaluation

Using infrastructure IPs to support SW-based self-test of processor cores