A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores

A Hybrid Approach for Detection and Correction of Transient Faults in SoCs

A Low-Cost Emulation System for Fast Co-verification and Debug

A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries

A SBST strategy to test microprocessors' Branch Target Buffer

A System-layer Infrastructure for SoC Diagnosis

A Top-Down Constraint-Driven Methodology for Smart System Design

A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors

article published in 2013

A novel scalable and reconfigurable emulation platform for embedded systems verification

A programmable BIST for DRAM testing and diagnosis

A software-based self-test methodology for system peripherals

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains

An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems

An Investigation on Pervasive Technologies for IoT-based Thermal Monitoring

scientific article published on 06 February 2019

An adaptive tester architecture for volume diagnosis

An on-line fault detection technique based on embedded debug features

Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts

Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study

Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs

Embedded Memory Diagnosis: An Industrial Workflow

Enabling Smart System design with the SMAC Platform

Evaluating Alpha-induced soft errors in embedded microprocessors

Evaluating the Impact of DfM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core

Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core

Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors

Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores

Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores

Functional Verification of DMA Controllers

article published in 2011

Functional test generation for DMA controllers

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

Integrating BIST techniques for on-line SoC testing

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores

On the Automation of the Test Flow of Complex SoCs

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors

On the use of embedded debug features for permanent and transient fault resilience in microprocessors

On-line software-based self-test of the Address Calculation Unit in RISC processors

Safety Evaluation of NanoFabrics

Software-Based Testing for System Peripherals

System-in-package testing: problems and solutions

Towards Multi-Domain and Multi-Physical Electronic Design