Search filters

List of works by Antonio Calomarde

A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits

A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

A new probabilistic design methodology of nanoscale digital circuits

A single event transient hardening circuit design technique based on strengthening

All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator

All-digital self-adaptive PVTA variation aware clock generation system for DFS

article published in 2014

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

Impact of FinFET and III–V/Ge Technology on Logic and Memory Cell Behavior

New redundant logic design concept for high noise and low voltage scenarios

Novel redundant logic design for noisy low voltage scenarios

PVTA Tolerant Self-adaptive Clock Generation Architecture

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

article published in 2014

Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

Variability Influence on FinFET-Based On-Chip Memory Data Paths

Variability impact on on-chip memory data paths

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Paulina is supported by:

About Paulina

Help