List of works - Luis Entrena

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

SET Emulation Considering Electrical Masking Effects

article by Luis Entrena et al published August 2009 in IEEE Transactions on Nuclear Science

Extensive SEU impact analysis of a PIC microprocessor for selective hardening

article published in 2009

Autonomous transient fault emulation on FPGAs for accelerating fault grading

article published in 2005

Information technology security using cryptography

scholarly article by Raul Sanchez-Reillo et al published June 2003 in IEEE Aerospace and Electronic Systems Magazine

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Increasing security with correlation-based fingerprint matching

A functional validation methodology based on error models for measuring the quality of digital integrated circuits

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects

article by Luis Entrena et al published August 2012 in IEEE Transactions on Nuclear Science

Study on the effect of multiple errors in robust systems based on critical task distribution

SET Emulation Under a Quantized Delay Model

A recovery mechanism for SET protection using standard-cells

scholarly article published September 2011

Sensitivity Evaluation Method for Aerospace Digital Systems With Collaborative Hardening

SET Emulation Under a Quantized Delay Model

Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC

A complete hardening method for the generation of fault tolerant circuits

scholarly article published 30 June 2005

Low-power design in aerospace circuits: A case study

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Integrated circuit debug through FPGA emulation: application to a PIC-18 macrocell

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques

article

Comparative of software-based hardening techniques for LEON 3 microprocessor

Efficient mitigation of data and control flow errors in microprocessors

Constrained placement methodology for reducing SER under single-event-induced charge sharing effects

scholarly article published September 2011

A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors

An autonomous FPGA-based emulation system for fast fault tolerant evaluation

Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening

Briefing power/reliability optimization in embedded software design

Fast SER evaluation of embedded RAMs in fault emulation systems

In-depth analysis of digital circuits against soft errors for selective hardening

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation

Robust cryptographic ciphers with on-line statistical properties validation

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness

Low power data processing system with self-reconfigurable architecture

High performance FPGA-based image correlation

Improvement in Security Evaluation of Biometric Systems

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

AKARI-X: A pseudorandom number generator for secure lightweight systems

Analysis of Turbo Decoder Robustness Against SEU Effects

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution

Logic Transformations by Multiple Wire Network Addition

article

Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers

scholarly article published June 2009

A Co-Design Approach for SET Mitigation in Embedded Systems

Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard

scholarly article published July 2008

FPGA-Based Acceleration of Fingerprint Minutiae Matching

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

List of works by Luis Entrena

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

SET Emulation Considering Electrical Masking Effects

Extensive SEU impact analysis of a PIC microprocessor for selective hardening

Autonomous transient fault emulation on FPGAs for accelerating fault grading

Information technology security using cryptography

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Increasing security with correlation-based fingerprint matching

A functional validation methodology based on error models for measuring the quality of digital integrated circuits

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects

Study on the effect of multiple errors in robust systems based on critical task distribution

SET Emulation Under a Quantized Delay Model

A recovery mechanism for SET protection using standard-cells

Sensitivity Evaluation Method for Aerospace Digital Systems With Collaborative Hardening

SET Emulation Under a Quantized Delay Model

Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC

A complete hardening method for the generation of fault tolerant circuits

Low-power design in aerospace circuits: A case study

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications

Integrated circuit debug through FPGA emulation: application to a PIC-18 macrocell

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques

Comparative of software-based hardening techniques for LEON 3 microprocessor

Efficient mitigation of data and control flow errors in microprocessors

Constrained placement methodology for reducing SER under single-event-induced charge sharing effects

A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors

An autonomous FPGA-based emulation system for fast fault tolerant evaluation

Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening

Briefing power/reliability optimization in embedded software design

Fast SER evaluation of embedded RAMs in fault emulation systems

In-depth analysis of digital circuits against soft errors for selective hardening

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation

Robust cryptographic ciphers with on-line statistical properties validation

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness

Low power data processing system with self-reconfigurable architecture

High performance FPGA-based image correlation

Improvement in Security Evaluation of Biometric Systems

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

AKARI-X: A pseudorandom number generator for secure lightweight systems

Analysis of Turbo Decoder Robustness Against SEU Effects

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution

Logic Transformations by Multiple Wire Network Addition

Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers

A Co-Design Approach for SET Mitigation in Embedded Systems

Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard

FPGA-Based Acceleration of Fingerprint Minutiae Matching

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection