A Programmable Adaptive Router for a GALS Parallel System

A novel approach to data integrity auditing in PCS: Minimising any Trust on Third Parties (DIA-MTTP)

scientific article published on 07 January 2021

AMULET1: an asynchronous ARM microprocessor

AMULET3 revealed

AMULET3i-an asynchronous system-on-chip

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

An asynchronous copy-back cache architecture

An asynchronous victim cache

Asynchronous and Self-Timed Processor Design

Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation

Automatic Controller Detection for Large Scale RTL Designs

Automatic data path extraction in large-scale register-transfer level designs

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

Designing robust asynchronous circuit components

Dynamic voltage and frequency scaling for neuromorphic many-core systems

article published in 2017

Fault Tolerant Delay Insensitive Inter-chip Communication

scholarly article published May 2009

Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip

article by Guangda Zhang et al published November 2017 in IEEE Transactions on Very Large Scale Integration Systems

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

scholarly article published May 2017

Network traffic exploration on a many-core computing platform: SpiNNaker real-time traffic visualiser

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip

Overview of the SpiNNaker System Architecture

article by Steve B. Furber et al published December 2013 in IEEE Transactions on Computers

Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application

scientific article published on 16 July 2018

Parallel Hardware Merge Sorter

Power management in the Amulet microprocessors

SpiNNaker

SpiNNaker - programming model

article

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation

The Amulet chips: Architectural development for asynchronous microprocessors

scholarly article published December 2009

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code