A Case Study of Hybrid Dataflow and Shared-Memory Programming Models: Dependency-Based Parallel Game Engine

A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions

A Data Flow Language to Develop High Performance Computing DSLs

A Hybrid Web Server Architecture for Secure e-Business Web Applications

article by Vicenç Beltran et al published 2005 in Lecture Notes in Computer Science

A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor

A Proposal for Error Handling in OpenMP

article by Alejandro Duran et al published 28 June 2007 in International Journal of Parallel Programming

A Proposal for Task Parallelism in OpenMP

A Proposal for User-Defined Reductions in OpenMP

A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures

article

A Proposal to Extend the OpenMP Tasking Model with Dependent Tasks

article published in 2009

A hybrid connector for efficient web servers

A methodology for the evaluation of high response time on E-commerce users and sales

A survey on performance management for internet applications

A template system for the efficient compilation of domain abstractions onto reconfigurable computers

ACOTES Project: Advanced Compiler Technologies for Embedded Streaming

ALOJA: A systematic study of Hadoop deployment variables to enable automated characterization of cost-effectiveness

AMA: Asynchronous Management of Accelerators for Task-based Programming Models

AMC: Advanced Multi-accelerator Controller

AMMC: Advanced Multi-Core Memory Controller

AXIOM: A Hardware-Software Platform for Cyber Physical Systems

Accurate energy accounting for shared virtualized environments using PMC-based power modeling techniques

Achieving high memory performance from heterogeneous architectures with the SARC programming model

Adaptive MapReduce Scheduling in Shared Environments

Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories

Advanced Pattern based Memory Controller for FPGA based HPC applications

Aeneas: A Tool to Enable Applications to Effectively Use Non-relational Databases

article published in 2013

Align and distribute-based linear loop transformations

An Experimental Evaluation of the New OpenMP Tasking Model

An Extension of the StarSs Programming Model for Platforms with Multiple GPUs

An Extension to Improve OpenMP Tasking Control

An approach to task-based parallel programming for undergraduate students

Analysis of Task Offloading for Accelerators

Analyzing Performance Improvements and Energy Savings in Infiniband Architecture using Network Compression

Analyzing reference patterns in automatic data distribution tools

Artificial Intelligence to Identify Retinal Fundus Images, Quality Validation, Laterality Evaluation, Macular Degeneration, and Suspected Glaucoma

scientific article published on 13 February 2020

Assessing Accelerator-Based HPC Reverse Time Migration

Assessing the Impact of Network Compression on Molecular Dynamics and Finite Element Methods

Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers

scholarly article by Luc Jaulmes et al published 1 September 2018 in IEEE Transactions on Parallel and Distributed Systems

Atomic quake

Automatic Exploration of Potential Parallelism in Sequential Applications

Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture

Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture

Autonomic Placement of Mixed Batch and Transactional Workloads

BSArc

BSC Vision Towards Exascale

Barcelona OpenMP Tasks Suite: A Set of Benchmarks Targeting the Exploitation of Task Parallelism in OpenMP

Batch Job Profiling and Adaptive Profile Enforcement for Virtualized Environments

Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors

CATA: Criticality Aware Task Acceleration for Multicore Processors

CUDAlign 3.0: Parallel Biological Sequence Comparison in Large GPU Clusters

CellMT: A cooperative multithreading library for the Cell/B.E

Characterization of workload and resource consumption for an online travel and booking site

Characterizing and Improving the Performance of Many-Core Task-Based Parallel Programming Runtimes

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

Conflict-free access to streams in multiprocessor systems

Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures

D8-tree

DMA++: On the Fly Data Realignment for On-Chip Memories

article by Nikola Vujic et al published February 2012 in IEEE Transactions on Computers

DMA-circular

DaSH: A benchmark suite for hybrid dataflow and shared memory programming models

DaSH: a benchmark suite for hybrid dataflow and shared memory programming models

Data distribution and loop parallelization for shared-memory multiprocessors

Decomposable and responsive power models for multicore processors using performance counters

Design space exploration for aggressive core replication schemes in CMPs

Designing an overload control strategy for secure e-commerce applications

Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling

Dynamic CPU provisioning for self-managed secure web applications in SMP hosting platforms

Dynamic Memory Instruction Bypassing

Effective communication and computation overlap with hybrid MPI/SMPSs

scholarly article published 2010

Effective communication and computation overlap with hybrid MPI/SMPSs

Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications

article

Enabling Distributed Key-Value Stores with Low Latency-Impact Snapshot Support

Enabling Resource Sharing between Transactional and Batch Workloads Using Dynamic Application Placement

Energy accounting for shared virtualized environments under DVFS using PMC-based power models

Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads

Evaluation of memory performance on the cell BE with the SARC programming model

article published in 2008

Experiences of Using Cassandra for Molecular Dynamics Simulations

article

Exploiting asynchrony from exact forward recovery for DUE in iterative solvers

Exploiting memory customization in FPGA for 3D stencil computations

Exploiting parallelism through directives on the nano-threads programming model

Exploring dynamic parallelism in OpenMP

article

Extending OpenMP to Survive the Heterogeneous Multi-Core Era

FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators

scholarly article published August 2010

Fine-grain parallel megabase sequence comparison with multiple heterogeneous GPUs

scientific article (publication date: 2014)

General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models

Guest Editors Introduction: Special Issue on OpenMP

Guest Editors’ Introduction

Guest Editors’ Introduction

Hardware-software coherence protocol for the coexistence of caches and local memories

Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories

article published in 2015

Hierarchical Task-Based Programming With StarSs

Hybrid access-specific software cache techniques for the cell BE architecture

scholarly article published 2008

Impact of the Memory Hierarchy on Shared Memory Architectures in Multicore Programming Models

Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool

Implementing OmpSs support for regions of data in architectures with multiple address spaces

Improving Web Server Performance Through Main Memory Compression

Improving disk bandwidth-bound applications through main memory compression

scholarly article published 2007

Improving the Integration of Task Nesting and Dependencies in OpenMP

Integrating Dataflow Abstractions into the Shared Memory Model

Introducing Speculative Optimizations in Task Dataflow with Language Extensions and Runtime Support

Introduction

Introduction

Introduction

Leveraging OmpSs to Exploit Hardware Accelerators

MAPC: Memory access pattern based controller

MUSA: A Multi-level Simulation Approach for Next-Generation HPC Machines

Managing SLAs of heterogeneous workloads using dynamic application placement

Mapping stream programs onto heterogeneous multiprocessor systems

Multimedia Big Data Computing for In-Depth Event Analysis

Multiple Target Task Sharing Support for the OpenMP Accelerator Model

Multithreaded software transactional memory and OpenMP

Nebelung: Execution Environment for Transactional OpenMP

Non-intrusive Estimation of QoS Degradation Impact on E-Commerce User Satisfaction

On the Instrumentation of OpenMP and OmpSs Tasking Constructs

article

On the maturity of parallel applications for asymmetric multi-core processors

OpenMP Extensions for Thread Groups and Their Run-Time Support

OpenMP extensions for FPGA accelerators

OpenMP tasking analysis for programmers

OpenMP tasks in IBM XL compilers

Optimizing resource utilization with software-based temporal multi-threading (stmt)

Optimizing the Exploitation of Multicore Processors and GPUs with OpenMP and OpenCL

article published in 2011

Overlapping communication and computation by using a hybrid MPI/SMPSs approach

scholarly article published 2010

PAMS: Pattern Aware Memory System for embedded systems

PARSECSs

PMSS: A programmable memory system and scheduler for complex memory patterns

POSTER

POSTER

POSTER: Profit-aware cloud resource provisioner for ecommerce

POTRA

PPMC: A Programmable Pattern Based Memory Controller

PPMC: Hardware scheduling and memory management support for multi accelerators

PVMC: Programmable Vector Memory Controller

ParaView + Alya + D8tree: Integrating High Performance Computing and High Performance Data Analytics

Partitioning the statement per iteration space using non-singular matrices

Performance Management of Accelerated MapReduce Workloads in Heterogeneous Clusters

Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models

Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models

Poster

Power-efficient VLIW design using clustering and widening

Productive Cluster Programming with OmpSs

Productive Programming of GPU Clusters with OmpSs

Programmability and portability for exascale: Top down programming methodology and tools with StarSs

QuakeTM

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

Reducing data access latency in SDSM systems using runtime optimizations

Reinforcement Learning-based Adaptive Mitigation of Uncorrected DRAM Errors in the Field

scientific article published on 30 August 2024

Resource-Aware Adaptive Scheduling for MapReduce Clusters

Runtime Address Space Computation for SDSM Systems

Runtime-Aware Architectures

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

scholarly article published 2016

SSMART

Sampled Simulation of Task-Based Programs

article

Scalability and Parallel Execution of OmpSs-OpenCL Tasks on Heterogeneous CPU-GPU Environment

Scaling Crowd Simulations in a GPU Accelerated Cluster

Scheduler-Activated Dynamic Page Migration for Multiprogrammed DSM Multiprocessors

Scheduling in a continuous area-time design space

article published in 1991

Self-Adaptive OmpSs Tasks in Heterogeneous Environments

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

Spark deployment and performance evaluation on the MareNostrum supercomputer

Special Issue on OpenMP—Guest Editors’ Introduction

Speeding Up Distributed MapReduce Applications Using Hardware Accelerators

Stand-Alone Memory Controller for Graphics System

Starsscheck: A Tool to Find Errors in Task-Based Parallel Programs

Strategies for the efficient exploitation of loop-level parallelism in Java

Support for OpenMP tasks in Nanos v4

Supporting Adaptive Privatization Techniques for Irregular Array Reductions in Task-Parallel Programming Models

Supporting stateful tasks in a dataflow graph

scholarly article

TARCAD: A template architecture for reconfigurable accelerator designs

Tareador

article

Task Superscalar: An Out-of-Order Task Pipeline

Task-based parallel breadth-first search in heterogeneous environments

The AXIOM Project: IoT on Heterogeneous Embedded Platforms

scientific article published in 2021

The AXIOM Software Layers

The AXIOM platform for next-generation cyber physical systems

The AXIOM project (Agile, eXtensible, fast I/O Module)

The AXIOM software layers

The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors

The Mont-Blanc Prototype: An Alternative Approach for HPC Systems

The Secrets of the Accelerators Unveiled: Tracing Heterogeneous Executions Through OMPT

article

Topic 11: Multicore and Manycore Programming

Towards Task-Parallel Reductions in OpenMP

article published in 2015

Transactional Access to Shared Memory in StarSs, a Task Based Programming Model

Transactional Memory and OpenMP

Transactional Memory: An Overview

Turbocharging boosted transactions or

Understanding tuning complexity in multithreaded and hybrid web servers

Unrolling Loops Containing Task Parallelism

Utility-based placement of dynamic Web applications with fairness goals

WormBench