A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

A new probabilistic design methodology of nanoscale digital circuits

A single event transient hardening circuit design technique based on strengthening

All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator

All-digital self-adaptive PVTA variation aware clock generation system for DFS

article published in 2014

Analysis and modelling of parasitic substrate coupling in CMOS circuits

Analysis of Direct Discharge Circuit to Power Autonomous Wear-able Devices using PVDF Piezoelectric Films

Analysis of dissipation energy of switching digital CMOS gates with coupled outputs

Appropriate charge control of the storage capacitor in a piezoelectric energy harvesting device for discontinuous load operation

Crosstalk effects between metal and polysilicon lines in CMOS integrated circuits

Data Dependence of Delay Distribution for a Planar Bus

Desigining Circuits from Imperfect Components in VISI Giga-scale Technologies

Design of complex circuits using the Via-Configurable transistor array regular layout fabric

article

Electronic System Design Paradigms in the Technologies of the Year 2020

Error probability in synchronous digital circuits due to power supply noise

Evaluation of layout design styles using a quality design metric

scholarly article published September 2012

Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

article

Ground bounce modelling for digital gigascale integrated circuits

Identification of micro-scale calorimetric devices

Lithography Aware Regular Cell Design Based on a Predictive Technology Model

article

Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Logic synthesis for manufacturability considering regularity and lithography printability

Measurements of Process Variability in 40-nm Regular and Nonregular Layouts

article published in 2014

Methodology of detection of spurious signals in VLSI circuits

Monitor strategies for variability reduction considering correlation between power and timing variability

New redundant logic design concept for high noise and low voltage scenarios

Noise generation and coupling mechanisms in deep-submicron ICs

Novel redundant logic design for noisy low voltage scenarios

On Anomaly-Aware Structural Health Monitoring at the Extreme Edge

scientific article published in January 2023

Optimum Piezoelectric Bending Beam Structures for Energy Harvesting using Shoe Inserts

PVTA Tolerant Self-adaptive Clock Generation Architecture

Physics-Based Time-Domain Model of a Magnetic Induction Microgenerator

article

Power supply noise and logic error probability

Review of energy harvesting techniques and applications for microelectronics (Keynote Address)

article

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

article published in 2014

Spurious signals in digital CMOS VLSI circuits: a propagation analysis

System-Level Simulation of a Self-Powered Sensor with Piezoelectric Energy Harvesting

Systematic and random variability analysis of two different 6T-SRAM layout topologies

Transistor sizing in lithography-aware regular fabrics

article

Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

VCTA: A Via-Configurable Transistor Array regular fabric

article

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

scientific article published on 09 December 2022

Yield estimation model for lithography hotspot distortions

article published in 2013