3D NOC for many-core processors

A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation

A Designer's Rationale for Nanoelectronic Hardware Security Primitives

A Programmable Majority Logic Array Using Molecular Scale Electronics

A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications

A hierarchical 3-D floorplanning algorithm for many-core CMP networks

A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays

A low-power memristive neuromorphic circuit utilizing a global/local training mechanism

A mixed-signal approach to memristive neuromorphic system design

A practical hafnium-oxide memristor model suitable for circuit design and simulation

scholarly article published May 2017

A programming framework for neuromorphic systems with emerging technologies

A read-monitored write circuit for 1T1M multi-level memristor memories

A synchronized axon hillock neuron for memristive neuromorphic systems

A two-dimensional chaotic logic gate for improved computer security

A write-time based memristive PUF for hardware security applications

article

Adiabatic Quantum Computation Applied to Deep Learning Networks

article

Algorithm and Application Impacts of Programmable Plasticity in Spiking Neuromorphic Hardware

scientific article published on 28 August 2023

An Application Development Platform for neuromorphic computing

article

An Energy-Efficient Memristive Threshold Logic Circuit

article published in 2012

Analysis and Modeling of Electroforming in Transition Metal Oxide-Based Memristors and Its Impact on Crossbar Array Density

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

scientific article published on 09 March 2019

Author Correction: Dynamical nonlinear memory capacitance in biomimetic membranes

scientific article published on 21 August 2019

BSB training scheme implementation on memristor-based circuit

Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems

Design Considerations for Memristive Crossbar Physical Unclonable Functions

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

scholarly article published 2010

Design of Neuromorphic Architectures with Memristors

Design techniques for in-field memristor forming circuits

article published in 2017

Designing CMOS/molecular memories while considering device parameter variations

Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits

Dynamical nonlinear memory capacitance in biomimetic membranes

scientific article published on 19 July 2019

Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices

Exploiting memristance for low-energy neuromorphic computing hardware

Extensions and enhancements for the DANNA neuromorphic architecture

Fault Analysis-Based Logic Encryption

Foundations of memristor based PUF architectures

scholarly article published July 2013

Hardware realization of BSB recall function using memristor crossbar arrays

Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments

scholarly article published 15 June 2013

Highly-scalable 3D CLOS NOC for many-core CMPs

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors

Leveraging Memristive Systems in the Construction of Digital Logic Circuits

Memristive Ion Channel-Doped Biomembranes as Synaptic Mimics.

scientific article published on 26 March 2018

Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level

Memristor based programmable threshold logic array

Memristor crossbar based hardware realization of BSB recall function

Memristor crossbar-based neuromorphic computing system: a case study

scientific article published in October 2014

Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications

scholarly article by Jeyavijayan Rajendran et al published May 2015 in Proceedings of the IEEE

Nano-PPUF: A Memristor-Based Security Primitive

scholarly article published August 2012

Nanoelectronics and Hardware Security

Non-overlapping transition encoding for global on-chip interconnect

On designing circuit primitives for cortical processors with memristive hardware

On-chip characterization of molecular electronic devices using CMOS

article published in 2007

Overview: Memristive devices, circuits and systems

Parallel memristors: Improving variation tolerance in memristive digital circuits

article published in 2011

Performance analysis of a memristive crossbar PUF design

Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications

scientific article published in 2021

Power Profile Obfuscation Using Nanoscale Memristive Devices to Counter DPA Attacks

Reducing stray currents in molecular memory through data encoding

Robustness Analysis of a Memristive Crossbar PUF Against Modeling Attacks

Security Meets Nanoelectronics for Internet of Things Applications

Sneak path enabled authentication for memristive crossbar memories

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits

Testing molecular devices in CMOS/nano integrated circuits

scholarly article published August 2007

The Effect of Device Parameter Variations on Programmable Majority Logic Arrays