A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms

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A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects

A Recursive Paradigm to Solve Boolean Relations

A Region-Based Algorithm for Discovering Petri Nets from Event Logs

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A Symbolic Algorithm for the Synthesis of Bounded Petri Nets

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A case study for the verification of complex timed circuits: IPCMOS

A hierarchical approach for generating regular floorplans

A mechanism for reducing the cost of branches in RISC architectures

A multi-radix approach to asynchronous division

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A new look at the conditions for the synthesis of speed-independent circuits

A performance analytical model for Network-on-Chip with constant service time routers

A radix-16 SRT division unit with speculation of the quotient digits

A recursive paradigm to solve Boolean relations

A region-based theory for state assignment in speed-independent circuits

A retargetable and accurate methodology for logic-IP-internal electromigration assessment

A structural encoding technique for the synthesis of asynchronous circuits

An asynchronous architecture model for behavioral synthesis

An efficient unique state coding algorithm for signal transition graphs

Analytical Performance Modeling of Hierarchical Interconnect Fabrics

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors

article by Nikita Nikitin et al published October 2013 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Area-Optimal Transistor Folding for 1-D Gridded Cell Design

Automatic generation of synchronous test patterns for asynchronous circuits

Automating Synthesis of Asynchronous Communication Mechanisms

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Behavioral transformations to increase noise immunity in asynchronous specifications

Boolean Decomposition for AIG Optimization

Boolean decomposition using two-literal divisors

Bridging the gap between asynchronous design and designers

Brownian Circuits

CAD directions for high performance asynchronous circuits

Chairmen's introduction

Checking signal transition graph implementability by symbolic BDD traversal

Comments on 'Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories'

Coping with the variability of combinational logic delays

Correct-by-construction microarchitectural pipelining

Coupling asynchrony and interrupts: Place Chart Nets

Decomposition and technology mapping of speed-independent circuits using Boolean relations

Derivation of Non-structural Invariants of Petri Nets Using Abstract Interpretation

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Deriving Petri nets from finite transition systems

Design Automation of Real-Life Asynchronous Devices and Systems

Designing a branch target buffer for executing branches with zero time cost in a RISC processor

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

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Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models

Divide-and-Conquer Strategies for Process Mining

Division with speculation of quotient digits

Dominator-based partitioning for delay optimization

Dynamic RAM for on-chip instruction caches

Efficient encoding schemes for symbolic analysis of Petri nets

Elastic Circuits

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Elastic systems

Elasticity and Petri Nets

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Encoding Large Asynchronous Controllers With ILP Techniques

Evaluating 'A+B=K' conditions in constant time

Evaluation of A+B=K conditions without carry propagation

Exploiting the locality of memory references to reduce the address bus energy

Formal methods for the analysis and synthesis of nanometer-scale cellular arrays

Formal verification of safety properties in timed circuits

From molecular interactions to gates

From molecular interactions to gates: a systematic approach

From synchronous to asynchronous: an automatic approach

Genet: A Tool for the Synthesis and Mining of Petri Nets

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Glass: a graph-theoretical approach for global binding

Guest Editorial: Special Section on Asynchronous Circuits and Systems

Handshake protocols for de-synchronization

Hardware Synthesis for Asynchronous Communications Mechanisms

Hardware and Petri Nets Application to Asynchronous Circuit Design

Hardware primitives for the synthesis of multithreaded elastic systems

Hierarchical gate-level verification of speed-independent circuits

High-level synthesis techniques for reducing the activity of functional units

High-radix division and square-root with speculation

Individual flip-flops with gated clocks for low power datapaths

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Input/Output Compatibility of Reactive Systems

article published in 2002

Integrating formal verification in an online judge for e-Learning logic circuit design

Jutge.org : Characteristics and Experiences

Layout-Aware Gate Duplication and Buffer Insertion

Lazy transition systems

Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions

article published in 2002

Lazy transition systems: application to timing optimization of asynchronous circuits

Log-Based Simplification of Process Models

Logic decomposition of speed-independent circuits

Metastability in Better-Than-Worst-Case Designs

Methodology and tools for state encoding in asynchronous circuit synthesis

Microarchitectural Transformations Using Elasticity

Mining structured petri nets for the visualization of process behavior

scholarly article published 2016

Multi-level clustering for clock skew optimization

Narrowing the margins with elastic clocks

New Region-Based Algorithms for Deriving Bounded Petri Nets

scholarly article by Josep Carmona et al published March 2010 in IEEE Transactions on Computers

On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics

Optimal exploration of the unrolling degree for software pipelining

scholarly article by Fermı́n Sánchez et al published January 1999 in Journal of Systems Architecture

Performance analysis of concurrent systems with early evaluation

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Performance analysis of concurrent systems with early evaluation

Performance optimization of elastic systems using buffer resizing and buffer insertion

Petri net analysis using boolean manipulation

Physical planning for the architectural exploration of large-scale chip multiprocessors

scholarly article published April 2013

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs

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Process Discovery Algorithms Using Numerical Abstract Domains

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Process Mining Meets Abstract Interpretation

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Quasi-Static Scheduling of Independent Tasks for Reactive Systems

Quasi-static scheduling for concurrent architectures

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Quasi-static scheduling of independent tasks for reactive systems

RESIS: A new methodology for register optimization in software pipelining

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Reactive clocks with variability-tracking jitter

Reduced instruction buffer for RISC architectures

Resource-constrained pipelining based on loop transformations

article by F. Sánchez & Jordi Cortadella published September 1993 in Microprocessing and Microprogramming

Retiming and recycling for elastic systems with early evaluation

Ring Oscillator Clocks and Margins

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Scheduling Synchronous Elastic Designs

Scheduling and resource binding for low power

Session B2: Processor Architecture II

Specification Mining for Asynchronous Controllers

Speculation in elastic systems

State encoding of large asynchronous controllers

State-Based Encoding of Large Asynchronous Controllers

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

Static Timing Analysis

Stochastic and topologically aware electromigration analysis for clock skew

Structural Methods to Improve the Symbolic Analysis of Petri Nets

Structural methods for the synthesis of speed-independent circuits

article published in 1998

Symbolic analysis of bounded Petri nets

Symbolic performance analysis of elastic systems

Synchronous Elastic Circuits

Synchronous Elastic Circuits with Early Evaluation and Token Counterflow

Synchronous Elastic Networks

Synchronous elastic circuits with early evaluation and token counterflow

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Synthesis of Asynchronous Hardware from Petri Nets

Synthesis of Reactive Systems: Application to Asynchronous Circuit Design

Synthesis of asynchronous controllers using integer linear programming

Synthesis of synchronous elastic architectures

scholarly article published 2006

THE USE OF PETRI NETS FOR THE DESIGN AND VERIFICATION OF ASYNCHRONOUS CIRCUITS AND SYSTEMS

Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis

The Octahedron Abstract Domain

The octahedron abstract domain

Time elastic digital systems and Petri Nets

Time-constrained loop pipelining

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Timing-driven N-way decomposition

Timing-driven logic bi-decomposition

Verification of Concurrent Systems with Parametric Delays Using Octahedra

Verification of asynchronous circuits by BDD-based model checking of Petri nets

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Verification of timed circuits with symbolic delays

Working-zone encoding for reducing the energy in microprocessor address buses