A Brief History of Multiprocessors and EDA

A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking

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A FRAMEWORK FOR ANALYZING COMBINED LOAD-CARRYING-CAPACITY OF PLUG-IN ELECTRIC VEHICLES AND SOLAR GENERATORS

A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications

A Framework for Analyzing Load-Carrying-Capacity of Plug-In Electric Vehicles and Impact on Solar Generators

A Functional Programming Framework for Latency Insensitive Protocol Validation

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A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms

A New Multi-threaded Code Synthesis Methodology and Tool for Correct-by-Construction Synthesis from Polychronous Specifications

A detailed analysis of the effective-load-carrying-capacity behavior of plug-in electric vehicles in the power grid

A hierarchical networked micro-simulator to study grid-integration of renewables and electric vehicles

A hierarchically distributed non-intrusive agent aided distance relaying protection scheme to supervise Zone 3

ADAPT: Adaptive Camouflage Based Deception Orchestration For Trapping Advanced Persistent Threats

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Abstraction of polychronous dataflow specifications into mode-automata

Accelerating SystemC simulations using GPUs

Accurate power estimation of hardware co-processors using system level simulation

Agent Based Supervision of Zone 3 Relays to Prevent Hidden Failure Based Tripping

Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS)

scholarly article by Gaurav Singh & Sandeep Shukla published 2007 in International Journal of Embedded Systems

Algorithms for power savings

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An Analysis of the Composition of Synchronous Systems

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An algorithm for inferring master agent rules in an agent based robust Zone 3 relay architecture

An alternative polychronous model and synthesis methodology for model-driven embedded software

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Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus

Analyzing Malicious Activities and Detecting Adversarial Behavior in Cryptocurrency based Permissionless Blockchains: An Ethereum Usecase

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Applying Verification Collaterals for Accurate Power Estimation

Assertion-Based Modal Power Estimation

C-Based Design of Heterogeneous Embedded Systems

Challenges of Rapidly Emerging Consumer Space Multiprocessors

Chapter 6 Probabilistic Analysis of Self-Assembled Molecular Networks

Co-simulating power systems and communication network for accurate modeling and simulation of PMU based wide area measurement systems using a global event scheduling technique

Communication network modeling and simulation for Wide Area Measurement applications

Comparing Reliability-Redundancy Tradeoffs for Two von Neumann Multiplexing Architectures

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Computing optimal solar penetration in the presence of plug-in electric vehicles

Constructive Polychronous Systems

Coprocessor design space exploration using high level synthesis

Cyber security impacts on all-PMU state estimator - a case study on co-simulation platform GECO

Dataflow Architectures for GALS

Design Issues for Networked Embedded Systems

Distributed Simulation of AADL Specifications in a Polychronous Model of Computation

EWD: A metamodeling driven customizable multi-MoC system modeling framework

Early Detection of Ransomware Activity based on Hardware Performance Counters

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Effects of property ordering in an incremental formal modeling methodology

Embedding Polychrony into Synchrony

Evaluating the grid impact of plug-in electric vehicles using dynamic commuting profiles

Expressing the Behavior of Three Very Different Concurrent Systems by Using Natural Extensions of Separation Logic

Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism

Fault- and Defect-Tolerant Architectures for Nanocomputing

Formal Verification of Hierarchically Distributed Agent Based Protection Scheme in Smart Grid

Formal transformation of a KPN specification to a GALS implementation

Generating Multi-Threaded code from Polychronous Specifications

Guest Editors' Introduction to the Special Section on Programming Architectures for Embedded Systems

Guest Editors' Introduction: GALS Design and Validation

Guest Editors' Introduction: Special Section on Science of Design for Safety Critical Systems

Guest Editors' Introduction: Special Section on System-Level Design and Validation of Heterogeneous Chip Multiprocessors

HORNSAT, model checking, verification and games

Heterogeneous Behavioral Hierarchy Extensions for SystemC

HiPeR - Early Detection of a Ransomware Attack using Hardware Performance Counters

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High Level Power Estimation Models for FPGAs

Identifying malicious accounts in blockchains using domain names and associated temporal properties

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Ingredients for Successful System Level Design Methodology

InviSeal: A Stealthy Dynamic Analysis Framework for Android Systems

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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

MCBCG: Model Checking Based Sequential Clock-Gating

MCF: A Metamodeling-Based Component Composition Framework—Composing SystemC IPs for Executable System Models

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MRICDF: A Polychronous Model for Embedded Software Synthesis

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Minimizing back pressure for latency insensitive system synthesis

Mining metadata for composability of IPs from SystemC IP library

Model Based Test Generation for Microprocessor Architecture Validation

Model Checking Bluespec Specified Hardware Designs

Model Checking Using Automata Theory

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Model-Driven Validation of SystemC Designs

Model-driven Validation of SystemC Designs

Model-driven test generation for system level validation

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Model-driven validation of SystemC designs

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

Networking technologies for wide-area measurement applications

On Cosimulating Multiple Abstraction-Level System-Level Models

On Model-Based Software Development

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On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications

On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study

On the Polychronous Approach to Embedded Software Design

On the complexity of relational problems for finite state processes

Online strategies for dynamic power management in systems with multiple power-saving states

Optimization of back pressure and throughput for latency insensitive systems

Parallelizing High-Level Synthesis

Power Aware High Level Synthesis of Hardware Coprocessors

Power estimation methodology for a high-level synthesis framework

Power system and communication network co-simulation for smart grid applications

Preface

Preface

Preface

Preface

Programming Models for Multi-Core Embedded Software

Reliability Analysis of Large Circuits Using Scalable Techniques and Tools

Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions

SCoPE : Statistical Regression Based Power Models for Co-Processors Power Estimation

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system

SMT based false causal loop detection during code synthesis from Polychronous specifications

Scalable techniques and tools for reliability analysis of large circuits

Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems

Structural Component Composition for System-Level Models

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Structured Component Composition Frameworks for Embedded System Design

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System level simulation guided approach to improve the efficacy of clock-gating

TTPHunter: Automated Extraction of Actionable Intelligence as TTPs from Narrative Threat Reports

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Tactics, Techniques and Procedures of Cybercrime: A Methodology and Tool for Cybercrime Investigation Process

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Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications

The Model Checking View to Clock Gating and Operand Isolation

Translating concurrent action oriented specifications to synchronous guarded actions

Translating concurrent action oriented specifications to synchronous guarded actions

Understanding Rug Pulls: An In-depth Behavioral Analysis of Fraudulent NFT Creators

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Unification and matching in process algebras

scholarly article by Qing Guo et al published 1998 in Lecture Notes in Computer Science

Using probabilistic model checking for dynamic power management

Verifying Compiler Based Refinement of Bluespec TM Specifications Using the SPIN Model Checker

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Verifying Peak Power Optimizations Using SPIN Model Checker

XFM

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