A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques

A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

article

A Flexible Framework for the Automatic Generation of SBST Programs

A Functional Approach for Testing the Reorder Buffer Memory

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing

A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms

A Hybrid Approach for Detection and Correction of Transient Faults in SoCs

A Hybrid Approach to Fault Detection and Correction in SoCs

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

A Low-Cost Emulation System for Fast Co-verification and Debug

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments

scientific article

A New Approach to Software-Implemented Fault Tolerance

A New Approach to the Analysis of Single Event Transients in VLSI Circuits

A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing

scholarly article published November 2011

A New Fault Injection Approach for Testing Network-on-Chips

A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring

A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

A P1500 compliant BIST-based approach to embedded RAM diagnosis

A P1500-compatible programmable BIST approach for the test of embedded flash memories

A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries

A SBST strategy to test microprocessors' Branch Target Buffer

A System-layer Infrastructure for SoC Diagnosis

A fault injection tool for SRAM-based FPGAs

A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors

article published in 2013

A genetic algorithm-based system for generating test programs for microprocessor IP cores

A hardware accelerated framework for the generation of design validation programs for SMT processors

A hierarchical approach for designing dependable systems

A low-cost susceptibility analysis methodology to selectively harden logic circuits

A methodology for test replacement solutions of obsolete processors

A new BIST architecture for low power circuits

scholarly article

A new functional fault model for FPGA application-oriented testing

A new hybrid fault detection technique for systems-on-a-chip

A new solution to on-line detection of Control Flow Errors

A novel scalable and reconfigurable emulation platform for embedded systems verification

A parallel system for test pattern generation

A programmable BIST for DRAM testing and diagnosis

A software fault tolerance method for safety-critical systems: effectiveness and drawbacks

A software-based methodology for the generation of peripheral test sets based on high-level descriptions

A software-based self-test methodology for system peripherals

A source-to-source compiler for generating dependable software

A suite of IEEE 1687 benchmark networks

A tester architecture suitable for MEMS calibration and testing

A transputer-based gate-level fault simulator

ARPIA: A High-Level Evolutionary Test Signal Generator

article published in 2001

About the functional test of permanent faults in distributed systems

Accurate and efficient analysis of single event transients in VLSI circuits

Accurate dependability analysis of CAN-based networked systems

Advanced Technologies for Transient Faults Detection and Compensation

Advanced techniques for GA-based sequential ATPGs

An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores

An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains

An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs

An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores

An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase

An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor

An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems

An Exact and Efficient Critical Path Tracing Algorithm

An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs

scholarly article published October 2009

An RT-level concurrent error detection technique for data dominated systems

An RT-level fault model with high gate level correlation

An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor

An adaptive tester architecture for volume diagnosis

An approach to sequential circuit diagnosis based on formal verification techniques

An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard

An effective ATPG flow for Gate Delay Faults

An effective approach for functional test programs compaction

An effective approach to automatic functional processor test generation for small-delay faults

An effective methodology for on-line testing of embedded microprocessors

An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores

An efficient fault simulation technique for transition faults in non-scan sequential circuits

An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs

An error-detection and self-repairing method for dynamically and partially reconfigurable systems

An improved data parallel algorithm for Boolean function manipulation using BDDs

An industrial environment for high-level fault-tolerant structures insertion and validation

An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers

An on-line fault detection technique based on embedded debug features

An optimized hybrid approach to provide fault detection and correction in SoCs

Analysis of SEU effects in a pipelined processor

Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts

Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables

Analysis of the equivalences and dominances of transient faults at the RT level

Analyzing SEU effects is SRAM-based FPGAsb

Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms

Approximate equivalence verification of sequential circuits via genetic algorithms

scholarly article

Assessing the diagnostic power of test pattern sets

Author index

Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Automatic Generation of Test Sets for SBST of Microprocessor IP Cores

Automatic Validation of Protocol Interfaces Described in VHDL

article by Fulvio Corno et al published 2000 in Lecture Notes in Computer Science

Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks

Automatic generation of validation stimuli for application-specific processors

Automatic test bench generation for validation of RT-level descriptions: an industrial experience

Automatic test generation for verifying microprocessors

Automatic test program generation from RT-level microprocessor descriptions

Automatic test program generation: a case study

Automatic test programs generation driven by internal performance counters

Automotive Microcontroller End-of-Line Test via Software-Based Methodologies

BASTION: Board and SoC test instrumentation for ageing and no failure found

Behavioral-level test vector generation for system-on-chip designs

C TPDL∗: Adapting TPDL∗ to concurrent simulation environments

Circular self-test path for FSMs

Code Generation for Functional Validation of Pipelined Microprocessors

Code generation for functional validation of pipelined microprocessors

Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study

Coupling different methodologies to validate obsolete microprocessors

Dependability analysis of CAN networks: an emulation-based approach

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture

Design validation of multithreaded architectures using concurrent threads evolution

Detailed comparison of dependability analyses performed at RT and gate levels

DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study

Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets

E-Learning at Politecnico di Torino

EXFI: a low-cost fault injection system for embedded microprocessor-based boards

Early evaluation of bus interconnects dependability for system-on-chip designs

Early reliability evaluation of a biomédical system

Early, accurate dependability analysis of CAN-based networked systems

Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs

Effective generation and evaluation of diagnostic SBST programs

Effectiveness and limitations of various software techniques for "soft error" detection: a comparative study

Efficient Techniques for Automatic Verification-Oriented Test Set Optimization

Efficient analysis of single event transients

Efficient estimation of SEU effects in SRAM-based FPGAs

Efficient machine-code test-program induction

Embedded Memory Diagnosis: An Industrial Workflow

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

Evaluating Alpha-induced soft errors in embedded microprocessors

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Evaluating system dependability in a co-design framework

Evaluating the Impact of DfM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core

Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures

Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results

Evolutionary test program induction for microprocessor design verification

Exact probabilistic testability measures for multi-output circuits

Experiences in the use of evolutionary techniques for testing digital circuits

Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors

Exploiting FPGA for accelerating fault injection experiments

Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors

Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores

Exploiting an I-IP for in-field SOC test

scientific article

Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug

Exploiting circuit emulation for fast hardness evaluation

Exploiting competing subpopulations for automatic generation of test sequences for digital circuits

Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores

Exploiting symbolic techniques for partial scan flip flop selection

Exploiting the debug interface to support on-line test of control flow errors

Expressing logical and temporal conditions in simulation environments: TPDL∗

article

Extended Fault Detection Techniques for Systems-on-Chip

FPGA-controlled PCBA power-on self-test using processor's debug features

Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption

Fast sequential circuit test generation using high-level and gate-level techniques

Fault Injection-based Reliability Evaluation of SoPCs

Fault injection analysis of transient faults in clustered VLIW processors

Fault injection in GPGPU cores to validate and debug robust parallel applications

Fault list compaction through static timing analysis for efficient fault injection experiments

Foreword

Foreword

Foreword

Fully automatic test program generation for microprocessor cores

Functional Verification of DMA Controllers

article published in 2011

Functional test generation for DMA controllers

Functional test generation for the pLRU replacement mechanism of embedded cache memories

GALLO: a genetic algorithm for floorplan area optimization

GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits

GPGPUs: How to combine high computational power with high reliability

Generating power-hungry test programs for power-aware validation of pipelined processors

Guaranteeing testability in re-encoding for low power

Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems

High Quality System Level Test and Diagnosis

High-level and hierarchical test sequence generation

High-level test generation for hardware testing and software validation

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Hybrid soft error detection by means of infrastructure IP cores [SoC implementation]

Hybrid soft error mitigation techniques for COTS processor-based systems

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

Identification and classification of single-event upsets in the configuration memory of sram-based fpgas

Impact of data cache memory on the single event upset-induced error rate of microprocessors

Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor

Improved software-based processor control-flow errors detection technique

Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study

In-field test of safety-critical systems: is functional test a feasible solution?

Increasing fault coverage during functional test in the operational phase

Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test

Industrial BIST of embedded RAMs

Initializability analysis of synchronous sequential circuits

Integrating BIST techniques for on-line SoC testing

Integrating online and offline testing of a switching memory

Introducing SW-based fault handling mechanisms to cope with EMI in embedded electronics: are they a good remedy?

MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test

Microprocessor Software-Based Self-Testing

scholarly article by Mihalis Psarakis et al published May 2010 in IEEE Design and Test of Computers

Microprocessor Testing: Functional Meets Structural Test

Multiple Errors Produced by Single Upsets in FPGA Configuration Memory: A Possible Solution

Neutron sensitivity and hardening strategies for Fast Fourier Transform on GPUs

article published in 2013

New Techniques to Reduce the Execution Time of Functional Test Programs

New evolutionary techniques for test-program generation for complex microprocessor cores

New techniques for accelerating fault injection in VHDL descriptions

New techniques for efficiently assessing reliability of SOCs

New techniques for speeding-up fault-injection campaigns

Observability solutions for in-field functional test of processor-based systems

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction

On test program compaction

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

scholarly article by Davide Sabena et al published April 2014 in IEEE Transactions on Very Large Scale Integration Systems

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores

On the Automation of the Test Flow of Complex SoCs

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

article

On the Functional Test of Branch Prediction Units

On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture

article by Ernesto Sanchez et al published 2012 in IFIP Advances in Information and Communication Technology

On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors

On the Generation of Functional Test Programs for the Cache Replacement Logic

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

On the detection of board delay faults through the execution of functional programs

On the development of Software-Based Self-Test methods for VLIW processors

article

On the development of diagnostic test programs for VLIW processors

article

On the diagnostic analysis of IEEE 1687 networks

On the evaluation of SEU sensitiveness in SRAM-based FPGAs

On the evaluation of soft-errors detection techniques for GPGPUs

On the functional test of L2 caches

On the functional test of MESI controllers

On the functional test of the BTB logic in pipelined and superscalar processors

On the functional test of the cache coherency logic in multi-core systems

On the generation of test programs for chip multi-thread computer architectures

On the in-field functional testing of decode units in pipelined RISC processors

On the in-field test of Branch Prediction Units using the correlated predictor mechanism

On the in-field test of embedded memories

On the maximization of the sustained switching activity in a processor

article published in 2015

On the on-line functional test of the Reorder Buffer memory in superscalar processors

On the optimization of SBST test program compaction

On the optimized generation of Software-Based Self-Test programs for VLIW processors

On the robustness of DCT-based compression algorithms for space applications

On the test of microprocessor IP cores

On the use of embedded debug features for permanent and transient fault resilience in microprocessors

On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core

On-line analysis and perturbation of CAN networks

On-line software-based self-test of the Address Calculation Unit in RISC processors

On-line testing of an off-the-shelf microprocessor board for safety-critical applications

Online Test of Control Flow Errors: A New Debug Interface-Based Approach

Online hardening of programs against SEUs and SETs

Optimal vector selection for low power BIST

Optimization of Self Checking FIR filters by means of Fault Injection Analysis

Optimized embedded memory diagnosis

Optimizing deceptive functions with the SG-Clans algorithm

Partition-Based Faults Diagnosis of a VLIW Processor

Peak Power Estimation: A Case Study on CPU Cores

Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture

Permanent faults on LIN networks: On-line test generation

Prediction of Power Requirements for High-Speed Circuits

Recovery scheme for hardening system on programmable chips

Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques

article published in 2014

Reducing test application time through interleaved scan

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAS

SAARA

SW-based transparent in-field memory testing

Safety Evaluation of NanoFabrics

Scan-Chain Intra-Cell Aware Testing

Scan-chain intra-cell defects grading

Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3–5, 2013

article

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders

Self-checking and fault tolerant approaches can help BIST fault coverage: a case study

scholarly article

Sequential circuit diagnosis based on formal verification techniques

Simulation-based analysis of SEU effects in SRAM-based FPGAs

Soft-error detection through software fault-tolerance techniques

Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs

Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications

article published in 2006

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

Software-Based Self-Test of Embedded Microprocessors

Software-Based Testing for System Peripherals

Software-Implemented Hardware Fault Tolerance

scholarly article published 2006

Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players?

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information

System safety through automatic high-level code transformations: an experimental evaluation

System-in-package testing: problems and solutions

TPDL: Extended temporal profile description language

Test Pattern Generation under Low Power Constraints

Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

Test Time Minimization in Reconfigurable Scan Networks

Test generation and coverage metrics

Test of Reconfigurable Modules in Scan Networks

Testability analysis and ATPG on behavioral RT-level VHDL

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study

The selfish gene algorithm

article

The training environment for the course on microprocessor systems at the Politecnico di Torino

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects

Transformation-based peak power reduction for test sequences

Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units

scientific article published on 14 November 2023

Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Using infrastructure IPs to support SW-based self-test of processor cores

Validation and robustness assessment of an automotive system

Validation of the dependability of CAN-based networked systems

Verifying the equivalence of sequential circuits with genetic algorithms

scholarly article