A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors

A Small and Effective Data Cache for Real-Time Multitasking Systems

A predictable hardware to exploit temporal reuse in real-time and embedded systems

A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings

ABS

ACDC

Analysis of network-on-chip topologies for cost-efficient chip multiprocessors

Avoiding the WCET Overestimation on LRU Instruction Cache

Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages

Characterization and cost-efficient selection of NoC topologies for general purpose CMPs

Characterization of Apache web server with Specweb2005

Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

article by Marta Ortin-Obon et al published July 2017 in IEEE Transactions on Very Large Scale Integration Systems

Delaying physical register allocation through virtual-physical registers

Dynamic construction of circuits for reactive traffic in homogeneous CMPs

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers

article by Benjamín Sahelices et al published January 2012 in Journal of Computer Science and Technology

Exploiting reuse locality on inclusive shared last-level caches

Filtering Directory Lookups in CMPs

Filtering Directory Lookups in CMPs with Write-Through Caches

Filtering directory lookups in CMPs

Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware

Hardware schemes for early register release

Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

article published in 2011

Late allocation and early release of physical registers

Low-Cost Adaptive Data Prefetching

Microarchitectural Support for Speculative Register Renaming

Modeling load address behaviour through recurrences

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems

Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs

Revisiting LP-NUCA Energy Consumption

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors

Software Demand, Hardware Supply

Speculative early register release

Store Buffer Design for Multibanked Data Caches

Store Buffer Design in First-Level Multibanked Data Caches

scholarly article

The reuse cache

Tradeoffs in buffering memory state for thread-level speculation in multiprocessors

Using software logging to support multiversion buffering in thread-level speculation