A 65-nm CMOS area optimized de-synchronization flow for sub-V T designs

A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip

A Multicore Processor for Time-Critical Applications

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

An Area-efficient Network Interface for a TDM-based Network-on-Chip

An area-efficient TDM NoC supporting reconfiguration for mode changes

Analytical derivation of traffic patterns in cache-coherent shared-memory systems

Analytical derivation of traffic patterns in shared memory architectures from Task Graphs

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

Asynchronous design of networks-on-chip

Avionics Applications on a Time-Predictable Chip-Multiprocessor

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

Can real-time systems benefit from dynamic partial reconfiguration?

Current trends in high-level synthesis of asynchronous circuits

Custom topology generation for network-on-chip

Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol

High-level synthesis for reduction of WCET in real-time systems

IR-drop reduction in sub-V T circuits by de-synchronization

Interfacing hardware accelerators to a time-division multiplexing network-on-chip

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

article

Open core protocol (OCP) clock domain crossing interfaces

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016

State-based Communication on Time-predictable Multicore Processors

scholarly article published 2016

Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools

T-CREST: Time-predictable multi-core architecture for embedded systems

article by Martin Schoeberl et al published October 2015 in Journal of Systems Architecture

The Argo NOC: Combining TDM and GALS

The ReNoC Reconfigurable Network-on-Chip

Timing Organization of a Real-Time Multicore Processor

Using dynamic partial reconfiguration of FPGAs in real-Time systems