A Basis for Formal Robustness Checking

A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit

A Highly Fault-Efficient SAT-Based ATPG Flow

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits

A PLiM Computer for the Internet of Things

A Synthesis Flow for Sequential Reversible Circuits

A better-than-worst-case robustness measure

A compact and efficient SAT encoding for quantum circuits

A fast untestability proof for SAT-based ATPG

A formal model for embedded brain reading

article

A general and exact routing methodology for Digital Microfluidic Biochips

A generic representation of CCSL time constraints for UML/MARTE models

A new SAT-based ATPG for generating highly compacted test sets

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

ACTion: combining logic synthesis and technology mapping for MUX based FPGAs

AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration

ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization

Adaptive Branch and Bound Using SAT to Estimate False Crosstalk

article

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

scientific article published in 2022

Advanced verification by automatic property generation

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization

An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata

An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions

An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits

An Integrated SystemC Debugging Environment

An MIG-based compiler for programmable logic-in-memory architectures

An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization

An evolutionary approach to reversible logic synthesis using output permutation

An exact method for design exploration of quantum-dot cellular automata

An improved branch and bound algorithm for exact bdd minimization

article by R. Ebendt et al published December 2003 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An improved gate library for logic synthesis of optical circuits

An integrated approach for combining BDD and SAT provers

Analyzing Functional Coverage in Bounded Model Checking

Analyzing Inconsistencies in UML/OCL Models

Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications

scientific article

Ancilla-free synthesis of large reversible functions using binary decision diagrams

Approximate BDD Minimization by Weighted A

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm

Approximate hardware generation using symbolic computer algebra employing grobner basis

scholarly article published March 2018

Approximation-aware rewriting of AIGs for error tolerant applications

Approximation-aware testing for approximate circuits

Assisted Behavior Driven Development Using Natural Language Processing

article

Atomic distributions in crystal structures solved by Boolean satisfiability techniques

article published in 2016

AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

scientific article published on 03 September 2024

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers

Automated and quality-driven requirements engineering

Automatic Fault Localization for Property Checking

Automatic Fault Localization for SystemC TLM Designs

Automatic Generation of Complex Properties for Hardware Designs

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata

Automatic Refinement Checking for Formal System Models

Automatic TLM Fault Localization for SystemC

article published in 2012

Automatic debugging of System-on-a-Chip designs

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications

Automatic property generation for the formal verification of bus bridges

Automatic refinement checking for formal system models

Automating the translation of assertions using natural language processing techniques

BDD circuit optimization for path delay fault testability

BDD minimization for approximate computing

BDD minimization using symmetries

article published in 1999

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits

BDD-based verification of scalable designs

Behavior Driven Development for circuit design and verification

article

Behaviour Driven Development for Tests and Verification

article

Benefits of illustrations and videos for technical documentations

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips

scholarly article published July 2017

Boolean function representation and spectral characterization using AND/OR graphs

Bounded fault tolerance checking

scientific article

Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems

CRAVE: An advanced constrained random verification environment for SystemC

scholarly article published October 2012

Change impact analysis for hardware designs from natural language to system level

CheckSyC: An Efficient Property Checker for RTL SystemC Designs

Checking concurrent behavior in UML/OCL models

Checking integrity during dynamic reordering in decision diagrams

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic

Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models

Co-synthesis of custom on-chip bus and memory for MPSoC architectures

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers

scholarly article published July 2018

Combining ordered best-first search with branch and bound for exact BDD minimization

article by R. Ebendt et al published October 2005 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Comparative Study by Solving the Test Compaction Problem

Compiled symbolic simulation for systemC

Complete Formal Verification of Multi Core Embedded Systems Using Bounded Model Checking

Completeness-Driven Development

article

Complexity of reversible circuits and their quantum implementations

article published in 2016

Cone of Influence Analysis at the Electronic System Level Using Machine Learning

scholarly article published September 2013

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing

Contradiction Analysis for Inconsistent Formal Models

Contradiction analysis for constraint-based random simulation

article

Coverage of OCL Operation Specifications and Invariants

Data extraction from SystemC designs using debug symbols and the SystemC API

Data flow testing for virtual prototypes

Debugging Contradictory Constraints in Constraint-Based Random Simulation

article

Debugging at the Electronic System Level

Debugging of Reversible Circuits Using pDDs

Debugging reversible circuits

Debugging sequential circuits using Boolean satisfiability

Decision diagram method for calculation of pruned Walsh transform

Decision diagram optimization using copy properties

Decision diagrams for the design of reversible and quantum circuits

Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs

Design reuse by modularity: a scalable dynamical (re)configurable multiprocessor system

Designing a RISC CPU in Reversible Logic

Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification

Determining minimal testsets for reversible circuits using Boolean satisfiability

Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits

article published in 2015

Dynamic minimization of word-level decision diagrams

EXOR transform of inputs to design efficient two-level AND/EXOR adders

article published in 2000

Early SoC security validation by VP-based static information flow analysis

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

scientific article published on 22 June 2022

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic

Effect of improved lower bounds in dynamic BDD reordering

Effective Robustness Analysis Using Bounded Model Checking Techniques

Effects of cell shapes on the routability of Digital Microfluidic Biochips

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts

Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion

Efficient Simulation-Based Debugging of Reversible Logic

Efficient minimization and manipulation of linearly transformed binary decision diagrams

Efficient synthesis of quantum circuits implementing clifford group operations

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation

article published in 2010

Embedding of Large Boolean Functions for Reversible Logic

Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models

Endurance management for resistive Logic-In-Memory computing architectures

scholarly article published March 2017

Enhancing debugging of multiple missing control errors in reversible logic

Enhancing robustness of sequential circuits using application-specific knowledge and formal methods

Ensuring safety and reliability of IP-based system design – A container approach

Envisioning self-verification of electronic systems

Equivalence Checking in Multi-level Quantum Systems

Equivalence Checking of Reversible Circuits

Equivalence checking using Gröbner bases

Error Bounded Exact BDD Minimization in Approximate Computing

Estimating Functional Coverage in Bounded Model Checking

article

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata

Evaluation of Cardinality Constraints on SMT-Based Debugging

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL

Exact BDD Minimization for Path-Related Objective Functions

Exact Design of Digital Microfluidic Biochips

article

Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques

article published in 2009

Exact One-pass Synthesis of Digital Microfluidic Biochips

article published in 2014

Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures

article published in 2014

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines

Exact Template Matching Using Boolean Satisfiability

Exact Toffoli Network Synthesis of Reversible Logic Using Boolean Satisfiability

Exact minimisation of path-related objective functions for binary decision diagrams

Exact routing for digital microfluidic biochips with temporary blockages

Exact routing for micro-electrode-dot-array digital microfluidic biochips

Exact routing with search space reduction

Exact sat-based toffoli network synthesis

Experimental Studies on SAT-Based ATPG for Gate Delay Faults

Exploiting reversibility in the complete simulation of reversible circuits

scholarly article published September 2013

Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits

scientific article published on 20 August 2024

Exploration of Sequential Depth by Evolutionary Algorithms

scholarly article

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata

Exploring superior structural materials using multi-objective optimization and formal techniques

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification

scientific article published on 10 June 2024

Extensions to the Reversible Hardware Description Language SyReC

Fast OFDD-based minimization of fixed polarity Reed-Muller expressions

Fast exact minimization of BDD's

Fault Detection in Parity Preserving Reversible Circuits

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits

article published in 2013

Foreword

Formal Specification Level

article published in 2015

Formal Specification Level

Formal methods for emerging technologies

Formal verification of word-level specifications

Frame conditions in symbolic representations of UML/OCL models

Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements

From Requirements and Scenarios to ESL Design in SystemC

From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits

scholarly article published May 2011

From biochips to quantum circuits: computer-aided design for emerging technologies

From reversible logic to quantum circuits: Logic design for an emerging technology

GREEDY IIP: partitioning large graphs by greedy iterative improvement

Gates vs. Splitters

Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL

article published in 2014

Generating and checking control logic in the HDL-based design of reversible circuits

Generating formal system models from natural language descriptions

Generation of optimal universal logic modules

Generic implementation of DD packages in MVL

Genetic algorithm for minimisation of fixed polarity Reed-Muller expressions

Grammar-based program generation based on model finding

Ground setting properties for an efficient translation of OCL in SMT-based model finding

Guided lightweight Software test qualification for IP integration using Virtual Prototypes

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking

article published in 2005

Hardware-Software Co-Visualization: Developing systems in the holodeck

scholarly article published April 2013

Hardware/Software Co-Visualization on the Electronic System Level Using SystemC

scholarly article published January 2016

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition

High Quality Test Pattern Generation and Boolean Satisfiability

History-based dynamic BDD minimization

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic

Improved Fault Diagnosis for Reversible Circuits

Improved SAT-based ATPG: More constraints, better compaction

Improved synthesis of Clifford+T quantum functionality

Improvements for constraint solving in the systemc verification library

article published in 2007

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs

Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation

Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms

Improving Test Pattern Compactness in SAT-based ATPG

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library

Improving the mapping of reversible circuits to quantum circuits using multiple target lines

Incorporating user preferences in many-objective optimization using relation ε-preferred

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

Incremental SAT Instance Generation for SAT-based ATPG

scholarly article published April 2008

Incremental Solving Techniques for SAT-based ATPG

Induction-Based Formal Verification of SystemC TLM Designs

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs

Instance Generation for SAT-based ATPG

scholarly article published 2007

Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules

Learning heuristics for OBDD minimization by Evolutionary Algorithms

scholarly article by Rolf Drechsler et al published 1996 in Lecture Notes in Computer Science

Level assignment for displaying combinational logic

Leveraging the Analysis for Invariant Independence in Formal System Models

article published in 2015

Lips: An IDE for model driven engineering based on natural language processing

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs

Logic Design Using Memristors: An Emerging Technology

Logic Minimization and Testability of 2-SPP Networks

Logic Synthesis for In-memory Computing Using Resistive Memories

Logic Synthesis for Majority Based In-Memory Computing

Logic Synthesis for RRAM-Based In-Memory Computing

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits

Low power optimization technique for BDD mapped circuits

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

Machine learning based test pattern analysis for localizing critical power activity areas

scholarly article published October 2017

Managing don't cares in Boolean satisfiability

Manipulation algorithms for K*BMDs

scholarly article by Rolf Drechsler et al published 1997 in Lecture Notes in Computer Science

Mapping NCV Circuits to Optimized Clifford+T Circuits

Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques

MetaSMT: a unified interface to SMT-LIB2

Minimal Stimuli Generation in Simulation-Based Verification

Minimization of OPKFDDs using genetic algorithms

scholarly article

Minimization of Word-Level Decision Diagrams

Minimization of free BDDs

Minimizing the number of one-paths in BDDs by an evolutionary algorithm

Minimizing the number of paths in BDDs

Minimizing the number of paths in BDDs: Theory and algorithm

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC

Modeling and proving functional completeness in formal verification of counting heads

More than true or false

scholarly article published 2017

Multi-Objective BDD Optimization with Evolutionary Algorithms

scholarly article published 2015

Multi-objective BDD optimization for RRAM based circuit design

Multi-objective Synthesis of Quantum Circuits Using Genetic Programming

Multi-output timed Shannon circuits

scholarly article

Natural Language Based Power Domain Partitioning

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation

OKFDD minimization by genetic algorithms with application to circuit design

OKFDDs versus OBDDs and OFDDs

OR-Inverter Graphs for the Synthesis of Optical Circuits

article

On Acceleration of SAT-Based ATPG for Industrial Designs

On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets

On local transformations and path delay fault testability

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study

On the Construction of Small Fully Testable Circuits with Low Depth

On the Difficulty of Inserting Trojans in Reversible Computing Architectures

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults

On the Relation Between BDDs and FDDs

article published in 1995

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study

On the complexity of design tasks for Digital Microfluidic Biochips

On the computational power of linearly transformed BDDs

On the construction of small fully testable circuits with low depth

On the generation of area-time optimal testable adders

On the relation between SAT and BDDs for equivalence checking

On variable ordering and decomposition type choice in OKFDDs

Optimal SWAP gate insertion for nearest neighbor quantum circuits

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression

Optimization-based multiple target test generation for highly compacted test sets

Optimizing DD-based synthesis of reversible circuits using negative control lines

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits

Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions

PASSAT 2.0: A multi-functional SAT-based testing framework

Panel: Future SoC verification methodology: UVM evolution or revolution?

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation

Polynomial datapath optimization using constraint solving and formal modelling

article published in 2010

Post-Verification Debugging of Hierarchical Designs

Post-verification debugging of hierarchical designs

Precise error determination of approximated components in sequential circuits with model checking

article

ProACt

Process variations aware robust on-chip bus architecture synthesis for MPSoCs

Processor Verification

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow

article published in 2008

Proving Completeness of Properties in Formal Verification of Counting Heads for Railways

Proving transaction and system-level properties of untimed SystemC TLM designs

Pseudo-Kronecker expressions for symmetric functions

QMDDs: Efficient Quantum Function Representation and Manipulation

Quality-Driven SystemC Design

scholarly article published 2010

Quantum Circuit Optimization by Hadamard Gate Reduction

Quantum circuits employing roots of the Pauli matrices

Quasi-Exact BDD Minimization Using Relaxed Best-First Search

RTL-datapath verification using integer linear programming

Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars

scientific article published on 09 August 2023

Reachability analysis for formal verification of SystemC

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Reconfigurable TAP controllers with embedded compression for large test data volume

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits

Recursive bi-partitioning of netlists for large number of partitions

Recursive bi-partitioning of netlists for large number of partitions

Reducing Reversible Circuit Cost by Adding Lines

Reducing the number of lines in reversible circuits

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling

article

Requirement Phrasing Assistance Using Automatic Quality Assessment

Requirements Engineering for Cyber-Physical Systems

Resilience evaluation via symbolic fault injection on intermediate code

Reusing Learned Information in SAT-based ATPG

RevKit: An Open Source Toolkit for the Design of Reversible Circuits

RevLib: An Online Resource for Reversible Functions and Reversible Circuits

RevVis: Visualization of Structures and Properties in Reversible Circuits

scholarly article by Robert Wille et al published 2014 in Lecture Notes in Computer Science

Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements

Reverse BDD-based synthesis for splitter-free optical circuits

Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology

Reversible Logic Synthesis with Output Permutation

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability

article by Arighna Deb et al published 27 June 2016 in ACM Journal on Emerging Technologies in Computing Systems

Reversible and Quantum Circuits

article published in 2016

Reversible circuit rewriting with simulated annealing

Reversible computation

RobuCheck

RobuCheck: A Robustness Checker for Digital Circuits

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

scholarly article published November 2010

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

Robustness Check for Multiple Faults Using Formal Techniques

Robustness and Usability in Modern Design Flows

article published in 2008

SAT-Lancer

SAT-based ATPG for reversible circuits

SMT-based Stimuli Generation in the SystemC Verification Library

SWORD: A SAT like Prover Using Word Level Information

SWORD: A SAT like prover using word level information

Safe IP Integration Using Container Modules

Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Scalable One-Pass Synthesis for Digital Microfluidic Biochips

Self-Verification as the Key Technology for Next Generation Electronic Systems

Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction

Simulation graphs for reverse engineering

article

Simulation-based equivalence checking between SystemC models at different levels of abstraction

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Spectral decision diagrams using graph transformations

Speeding up SAT-Based ATPG Using Dynamic Clause Activation

Structural heuristics for SAT-based ATPG

Stuck-At-Fault Testability of SPP Three-Level Logic Forms

SyCE: An Integrated Environment for System Design in SystemC

SyReC: A Programming Language for Synthesis of Reversible Circuits

scholarly article published 8 November 2011

SyReC: A hardware description language for the specification and synthesis of reversible circuits

SyReC: a programming language for synthesis of reversible circuits

scholarly article published 2010

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions

Synthesis of Fully Testable Circuits From BDDs

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages

article

Synthesis of Reversible Circuits Using Decision Diagrams

Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams

Synthesis of optical circuits using binary decision diagrams

Synthesis of quantum circuits for linear nearest neighbor architectures

article by Mehdi Saeedi et al published 19 October 2010 in Quantum Information Processing

Synthesis of reversible circuits with minimal lines for large functions

article

Synthesizing multiplier in reversible logic

System Exploration of SystemC Designs

System level validation using formal techniques

System-level validation using formal techniques

TLM protocol compliance checking at the Electronic System Level

article published in 2011

Technical Documentation of Software and Hardware in Embedded Systems

Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits

Test Pattern Generation using Boolean Proof Engines

Testability of SPP Three-Level Logic Networks in Static Fault Models

Testability of circuits derived from lattice diagrams

Testbench qualification for SystemC-AMS timed data flow models

The K*BMD: A verification data structure

The SyReC hardware description language: Enabling scalable synthesis of reversible circuits

The complexity of error metrics

scholarly article by Oliver Keszocze et al published November 2018 in Information Processing Letters

The complexity of the inclusion operation on OFDD's

The system verification methodology for advanced TLM verification

Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry

article by Christopher D. Rosebrock et al published June 2016 in Combustion and Flame

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines

Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws

Towards Fully Automatic Synthesis of Embedded Software

Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits

Towards Reversed Approximate Hardware Design

Towards Unifying Localization and Explanation for Automated Debugging

Towards VHDL-Based Design of Reversible Circuits

Towards a Design Flow for Reversible Logic

Towards a Verification Flow Across Abstraction Levels: Verifying Implementations Against Their Formal Specification

Towards a methodology for self-verification

Towards a model-based verification methodology for Complex Swarm Systems (Invited paper)

article

Towards analyzing functional coverage in SystemC TLM property checking

Towards automatic determination of problem bounds for object instantiation in static model verification

Towards automatic scenario generation from coverage information

Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach

scholarly article published September 2017

Towards fully automated TLM-to-RTL property refinement

Towards lightweight satisfiability solvers for self-verification

article

Towards verifying determinism of SystemC designs

Trading off circuit lines and gate costs in the synthesis of reversible logic

Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs

scholarly article published January 2017

Unintrusive aging analysis based on offline learning

Upper bounds for reversible circuits based on Young subgroups

scholarly article by Nabila Abdessaied et al published June 2014 in Information Processing Letters

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability

Using QBF to increase accuracy of SAT-based debugging

Using Word-Level Information in Formal Hardware Verification

Using a two-dimensional fault list for compact Automatic Test Pattern Generation

Using lower bounds during dynamic BDD minimization

Using unsatisfiable cores to debug multiple design errors

Validating SystemC Implementations Against Their Formal Specifications

Variable reordering for shared binary decision diagrams using output probabilities

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers

Verification of designs containing black boxes

Verification-Driven Design Across Abstraction Levels: A Case Study

Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation

Verifying SystemC using an intermediate verification language and symbolic simulation

Verifying SystemC using stateful symbolic simulation

Verifying consistency between activity diagrams and their corresponding OCL contracts

Verifying integrity of decision diagrams

Verifying next generation electronic systems

Weighted A∗ search – unifying view and application

Window optimization of reversible and quantum circuits

WoLFram- A Word Level Framework for Formal Verification

Yise - a novel framework for boolean networks using y-inverter graphs

metaSMT: focus on your application and not on solver integration