Search filters

Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Image Image of a generic work. The text above it indicates that there is no free image of the work available, and that if you own one, you can click on the placeholder link to upload it.
Description
Author/s

author: Takeshi Ohshima  Daisuke Kobayashi 

Publication date August 2009
Language
Country of origin
Wikipedia link
Copyright status
Missing/wrong data? Edit Wikidata item