A 1.5 ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent power savings.
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| Description | scientific article published in October 2013 |
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author: Bernabé Linares-Barranco María Teresa Serrano Gotarredona |
| Publication date | October 1, 2013 |
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| Missing/wrong data? | Edit Wikidata item |